1. Field of the Invention
The present invention relates to analog/digital information processing, and more particularly to digital-to-analog (D/A) converting techniques which can execute multiplication processing in a high accuracy by use of analog memories.
Although the present invention is principally utilized in D/A converters and particularly described herein in connection therewith, it should be understood that the present invention may be widely applied to a neural network circuit, a multiplier circuit, a signal processor and so on.
2. Description of the Related Art
While analog memory devices represented by a charge coupled device (CCD) and other charge transfer devices (CTD) have been widely spread in the form of imaging devices and delay lines, they are merely applied to limited fields of their original uses such as analog shift registers, analog memories and so on. Although the utilization of these analog memory devices in matched filters and multi-value logic circuits have been investigated, very few applications have been actually realized in the field of signal processing.
In general, the CCD has excellent characteristics such as less power consumption and high density of integration, so that the establishment of higher signal processing functions such as multiplication has been expected. However, very few specific approaches have been proposed for the present except for several examples, as will be mentioned below.
FIG. 1 shows in a schematic circuit diagram form an example of conventional CCD matched filters. The illustrated CCD matched filter adjusts the filter characteristics by a pair of floating electrode groups placed on a CCD analog shift register. Also, interactions between charge signals and the electrode areas on individual stages are indirectly utilized to parallelly execute analog multiplications at the respective stages, so that the calculating speed is relatively high. However, since errors in the electrode area directly affect the multiplication accuracy, the multiplication accuracy apparently tends to decrease as the miniaturization of circuits is advanced. It will therefore be understood that there is a certain limit in the highly dense integration.
As for the application of the CCD to multiple-valued logic circuits, basic logic processing is currently being investigated. A prospect of realizing high-grade processing, such as a multiplier utilizing the CCD as shown in FIG. 1, seems to be still indefinite. The application of the CCD in this field is described in an article entitled "Multiple-Valued VSLI and Systolic Array with CCD Realization" by J. Han, Progress in Computer-Aided VLSI Design, Vol. 3, Implementations, pp. 67-118, Ablex Publishing, Norwood, N.J., USA, 1989.
Although not included in the charge transfer device, there has been proposed and commercialized a method of realizing D/A and A/D conversion based on the charge re-distribution principle by applying "a switched capacitor circuit" which utilizes capacitance for an analog memory to perform signal processing (FIG. 2). However, with the switched capacitor circuit, it is indispensable to repetitively recharge and discharge capacitors in the circuit using a stable voltage source, so that required power consumption is much larger than that of the charge transfer device such as CCD. For this reason, it is generally thought that the implementation of the switched capacitor circuit in a high density integrated circuit and the enhancement of the operating speed are limited. The switched capacitor circuit further implies a number of disadvantages. For example, it cannot execute D/A conversion with a charge signal used directly as a reference signal. For further details about the switched capacitor circuit, refer to an article entitled "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques, Part II", by R. E. Sua'res, et al, IEEE, J. Solid-state Circuits, SC-10, 6. pp. 379-395 (Dec. 1975).
In addition, charge domain devices (CDD) have also been developed and studied for the purpose of analog signal processing such as a product sum operation for IIR (Infinite Impulse Response), FIR (Finite Impulse Response) and so on.
A technique employed for this processing is multiplication by a fixed coefficient. Specifically, a charge splitting technique constitutes the basis in which input charges are divided in a constant ratio in a charge domain. This technique is described in detail in an article entitled "Charge Packet Splitting in Charge Domain Devices" by S. S. Bencuya and A. J. Steckl, IEEE Trans. Electron Devices, Vol. ED-31, No. 10, pp 1494-1501, 1984. The disclosure of this article is herein incorporated by reference.
As described also in the above-mentioned article, the charge dividing ratio is extremely critical in this technique. Since the accuracy of the division depends on the geometric accuracy of a splitter, a larger splitter is required for achieving a higher accuracy. However, according to the article, even a large splitter having the width of 250 .mu.m merely provides an accuracy of approximately 0.18% (when divided in 1:1).
A multiplier based on the above-mentioned technique has drawbacks in that its charge dividing ratio is fixed and not adjustable, and a high accuracy is difficult to achieve. Thus, this technique is not advantageous over the digital signal processor (DSP), and therefore has been hardly widespread at present.
Further, investigations on a neural network using CCD has also been promoted. An example is described in "A CCD Programmable Signal Processor" by Alice M. Chiang, IEEE J. Solid-state Circuits, Vol. 25, No. 6, December 1990. The disclosure of this article is herein incorporated by reference.
This example employs a scheme in which a multiplication type D/A converter using the CCD technique is utilized as a multiplier, and an analog signal is multiplied by a digital coefficient. However, in Chiang, an input signal is not supplied as charges but as an analog voltage, and input gates having ratios of 1, 2, 4, . . . , 2.sup.n-1, respectively, are parallelly disposed and respectively controlled by digital signal bits. With this configuration, there is a drawback in that a multi-bit operation requires a large dimension of the device so that highly integrated devices cannot be expected. Also, since charge inputs cannot be directly processed, the accuracy will be limited at a relatively low value.